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Freescale Semiconductor /MK61F15WS /DDR /CR50

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Interpret as CR50

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0P2PRIRLX0RESERVED0 (0)CLKSTATUS 0RESERVED

CLKSTATUS=0

Description

DDR Control Register 50

Fields

P2PRIRLX

Port 2 Priority Relax
RESERVED

Reserved
CLKSTATUS

Clock Status

0 (0): Disabled

1 (1): Enabled
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data